• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    The invention relates to an image sensor comprising: at least one pixel having a photodiode (PD); a detection node (SN) coupled to the photodiode via a transfer gate (104); and another node (AN) coupled to the detection node (SN) via a first transistor (112); and a control circuit (120) adapted to: apply, during a reset operation of the voltage levels on the detection node (SN) and the other node (AN), a first voltage level (VDD) at a node controlling the first transistor (112); and applying, during a charge transfer operation from the photodiode (PD) to the detection node (SN), a second voltage level (VSK) at the control node of the first transistor (112), the second level of voltage being lower than the first voltage level and greater than a ground voltage of the pixel.
    公开号:FR3027479A1
    申请号:FR1460106
    申请日:2014-10-21
    公开日:2016-04-22
    发明作者:Marie Guillon；Yvon Cazaux；Puchades Josep Segura
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] 1 B13328 - DD15336JBD IMAGE SENSOR PIXEL HAVING MULTIPLE SENSOR KNOT GAINS Domain also referred to as "pinched photodiodes" and having sense node. BACKGROUND OF THE INVENTION CMOS image sensors generally comprise an image sensor, and a description particularly relates to one having pixels provided with photodiodes, the field of fixed potential image sensors, and multiple network gains. pixels each having a fixed photodiode which accumulates charges during a period of time. The accumulated charge is then transferred to a pixel detection before being read. The sensitivity of the circuit, as well as its dynamic range, depends partly on the size of the node's capacitance. node of such at least one detection. leads to high sensitivity, but low dynamic range. A relatively high capacity level leads to a high dynamic range, but low sensitivity. It is an ongoing challenge in the field of image sensors to obtain pixels having both a high sensitivity and a high dynamic range, without greatly increasing the size or power consumption of the image sensor. image sensor. SUMMARY An object of embodiments of the present disclosure is to at least partially solve one or more problems of the prior art. In one aspect, there is provided an image sensor comprising: at least one pixel having a photodiode; a detection node coupled to the photodiode via a transfer gate; and another node coupled to the detection node via a first transistor; and a control circuit adapted to: apply, during a reset operation of the voltage levels on the detection node and on the other node, a first voltage level to a control node of the first transistor; and applying, during a charge transfer operation from the photodiode to the detection node, a second voltage level at the control node of the first transistor, the second voltage level being lower than the first voltage level 20 and greater than a mass voltage of the pixel. According to one embodiment, the second voltage level is less than VRT + VTH and greater than VPD + VTH, where VRT is a reset voltage level applied to the sense node and the other node during the operation of 25. reset, VPD is a fixed voltage level of the photodiode and VTH is a threshold voltage level of the first transistor. According to one embodiment, during the transfer operation, the control circuit is further adapted to apply the first voltage level to a control node of the transfer gate. According to one embodiment, the control circuit is further adapted to: perform, after the transfer operation, a first read operation to generate a first value on the basis of the voltage on the detection node ; and comparing the first value to a threshold level. According to one embodiment, the control circuit is further adapted to perform a second read operation to generate a second value based on the voltage on the sense node during the application of the first voltage level to the node. control of the first transistor. According to one embodiment, the image sensor further comprises an output block coupled to the detection node 10 via a read circuit of the pixel, in which on the basis of the comparison of the first value with the threshold level, the output block is arranged to: generate a pixel value based on the first value; or generate a pixel value based on the second value. According to one embodiment, said at least one other pixel comprises a reset transistor having one of its main current nodes connected to the other node and its other main current node coupled to a supply voltage rail. . According to one embodiment, said at least one pixel further comprises a reset transistor having one of its main current nodes connected to the detection node and its other main current node coupled to a supply voltage rail. . According to one embodiment, said at least one pixel further comprises a second transfer gate coupled between the photodiode and a supply voltage rail. According to one embodiment, the control circuit is adapted to control the second transfer gate of said at least one pixel to reset the photodiode to perform a global reset of the image sensor. According to another aspect, there is provided a method for actuating at least one pixel of an image sensor, said at least one pixel comprising: a photodiode; a sense node 35 coupled to the photodiode through a transfer gate; and another node coupled to the detection node via a first transistor, the method comprising: applying, by a control circuit during a resetting operation the voltage levels on the detection node and the other node, a first voltage level on a control node of the first transistor; and applying, by the control circuit during a charge transfer operation from the photodiode to the detection node, a second voltage level at the control node of the first transistor, the second voltage level being lower than the first voltage level. voltage and greater than a ground voltage of the pixel. According to one embodiment, the second voltage level is less than VRT + VTH and greater than VPD + VTH, where VRT 15 is a reset voltage level applied to the sense node and the other node during the operation of reset, VPD is the set voltage level of the photodiode and VTH is a threshold level of the first transistor. According to one embodiment, the method further comprises applying, during the transfer operation, the second voltage level to the transfer gate. According to one embodiment, the method further comprises: performing, after the transfer operation, a first read operation to generate a first value based on the voltage on the detection node; and comparing the first value to a threshold level. According to one embodiment, the method further comprises: a second read operation for generating a second value based on the voltage on the detection node during the application of the first voltage level to the control node of the first transistor ; and based on comparing the first value at the threshold level: either generating a pixel value based on the first value; or generate a pixel value based on the second value.
    [0002] B13328 - DD15336JBD Brief description of the drawings The above-mentioned and other advantages will become apparent upon reading the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings, in which: FIG. 1 schematically illustrates a pixel according to an embodiment of the present description; Fig. 2 is a flowchart showing steps in an image; An operation method of an embodiment of a pixel of a sensor of the present description according to FIGS. 3A to 3E are diagrams representing the transfer of charges between nodes of the pixel of FIG. reset, transfer and read according to an exemplary embodiment; Fig. 4 is a graph showing the relationship between the accumulated charge and read voltage levels in the pixel of Fig. 1 according to an exemplary embodiment; Figure 5 schematically illustrates an output circuit of the pixel of Figure 1 in more detail according to an exemplary embodiment; and Fig. 6 is a timing diagram illustrating signals in a pixel during reset, transfer and read operations according to an exemplary embodiment. DETAILED DESCRIPTION In the following description, the term "connected" is used to refer to a direct connection between one element and another, while the term "coupled" implies that the connection 30 between the two elements may be direct, or may be via an intermediate element, such as a transistor, resistor or other component. Figure 1 schematically illustrates a pixel 100 of an image sensor according to an exemplary embodiment. The pixel 100 B13328 - DD15336JBD 6 is for example part of a network of a plurality of pixels arranged in rows and columns forming the image sensor. The pixel 100 comprises a fixed potential photodiode PD. As known in the art, the fixed potential photodiodes have their voltage set at a certain level, referred to herein as VPD. For example, the photodiode is set at a voltage of about 1.5 V, and more generally at a voltage of between 1 and 2 V. The fixed potential photodiode PD is coupled between the ground voltage and a node 102. The node 102 is further coupled to a pixel SN detection node via a transfer gate 104, which is for example controlled by a transfer gate signal TG. The detection node SN has a capacitance CSN, which results for example only parasitic capacitances of neighboring components, or which can result in addition to the capacitance of a capacitor C1 optionally coupled between the detection node SN and a voltage level. mass or virtual mass. In some embodiments, the CSN capacitance is relatively low, for example 10 fF or less. The detection node SN is further coupled to a reading circuit of the pixel. In the example of FIG. 1, the read circuit comprises a transistor 106 coupled in a source follower arrangement, with its control node coupled to the detection node SN, and its source coupled via a transistor 108 to an output column line 110 of the pixel. The transistor 106 has for example its drain coupled to a supply voltage VRT of the pixel. The transistor 108 is controlled by a read signal RD. In alternative embodiments, a different arrangement of the read circuit would be possible, for example with the read transistor 108 coupled between the drain of the transistor 106 and the supply voltage VRT. The pixel 100 further comprises an additional node 35 AN. The additional node AN is coupled to the detection node SN B13328 - DD15336JBD 7 via the main conduction nodes of a transistor 112, which is for example an NMOS transistor, and which has its control node coupled to receive a control signal SW. The additional node AN has a CAN capacitance, which results for example only parasitic capacitances of the surrounding components or which may result in addition to the capacitance of a capacitor O 2 coupled between the additional node AN and the ground or mass voltage level. Virtual. The CAN capacitance is for example greater than the CSN capacitance of the detection node SN, and is for example 10 fF or more. The capacitance CSN is for example chosen so that the combined capacitance CsN + CAN can support the maximum load that can be transferred from the photodiode PD. In some embodiments, the CAN capability is at least ten times greater than the CsN capability. The pixel 100 further comprises a transistor 116 coupled by its main conduction nodes between the supply voltage of the pixel VRT and either the additional node AN or the detection node SN. The transistor 116 is for example an NMOS transistor controlled at its control node by a reset signal RST. The pixel 100 may also include a transfer gate 118 coupled between the node 102 and the supply voltage VRT of the pixel. The transfer gate 118 receives an RTG signal to reset the voltage of the photodiode. The signals TG, RD, SW, RST and RTG intended to control the transistors / gates 104, 108, 112, 116 and 118 of the pixel are for example respectively provided by a control circuit (CTRL) 120. The control circuit 120 is for example common for a group of pixels of the image sensor, such as a row of pixels. The control circuit 120 receives for example a synchronization signal CLK, and is for example implemented by an ASIC (application-specific integrated circuit), although in alternative embodiments it could be at the B13328 - DD15336JBD 8 least partially implemented by a processor executing software instructions. FIG. 1 also illustrates an output block 122 coupled to the column line 110 and associated for example with a column of pixels. Output block 122 includes, for example, sample-and-hold circuits for sampling voltage levels read on pixel 100, and also includes circuitry for generating a PIX output pixel value based on the voltage levels read from the pixel as will be described in more detail below. The operation of the pixel of FIG. 1 will now be described in more detail with reference to the flowchart of FIG. 2. FIG. 2 illustrates operations performed by the pixel 100 and the output block 122 of FIG. controlling the control circuit 120 during image capture and playback. It is thus assumed that the circuit is powered, and that an image capture sequence has been triggered. For example, the image sensor is part of an image capture device, such as a camera, a mobile phone or the like, and a user of the image capture device has provided an input element to cause the capture an image or video. In an operation 202, an integration phase of the photodiode takes place. The integration phase is for example initiated by resetting the voltage of the photodiode by activating the signal RTG to activate the transfer gate 118 and couple the photodiode to the supply voltage VRT. The voltage on the node 102 is thus reset for example at the fixed voltage VPD of the photodiode. In alternative embodiments, the transfer gate 118 could be omitted, and the photodiode could be reset via another channel, for example by activating the transfer gate 104, after resetting the voltage on the node of SN detection at the VRT voltage. 3328 - DD15336JBD 9 A next operation 204 takes place at the end of the integration phase, and corresponds to a transfer operation. At a certain point before the transfer operation, a reset operation is performed to reset the voltage levels on the detection node SN and on the additional node AN. During this reset operation, a voltage level, for example VDD, is applied as voltage signals SW and RST on the control nodes of transistors 112 and 116, respectively, to make these transistors conductive, thereby to reset the two nodes SN and AN. During the transfer operation, the charge accumulated by the photodiode during the integration phase is transferred from the photodiode PD to the detection node SN by activating the transfer gate 104. For example, a supply voltage level VDD is applied to the transfer gate 104. Throughout the transfer operation, the voltage signal SW on the control node of the transistor 112 is at an intermediate voltage level VSK, also referred to herein as the skimming voltage level. which is greater than the ground voltage of the pixel and less than the supply voltage V DD. For example, the voltage VSK is greater than VPD + VTH, VPD being the fixed voltage level of the photodiode, and VTH being the threshold voltage of the transistor 112. The voltage level VSK is also for example at a level below VRT. + VTH, VRT being the level of the reset voltage applied to the detection node SN or to the additional node AN via the reset transistor 116. In other words, the level of VSK is for example set so that that the transistor 112 is conductive for a sub-range of the possible voltage levels of VsN as a result of a transfer operation. The effect of applying an intermediate voltage VSK to the control node of the transistor 112 is that, when the load on the detection node SN exceeds a certain level, it will overflow to the additional node AN. That is, the amount of negative charge transferred from the photodiode B13328-DD153363BD PD may cause a voltage drop on the detection node SN below the VSK level minus the threshold voltage VTH of the transistor 112, and so some of the negative charge will be transferred or "skimmed" from the detection node SN to the additional node AN until the voltage on the detection node SN is established at a level of VSK-VTH. In a subsequent operation 206, a first operation of reading the voltage VsN on the detection node SN is carried out, with the signal SW still at the level of VSK. If during the transfer operation no load has been skimmed from the detection node SN to the additional node AN, the voltage VsN will be equal to at least VSK -VTH. More specifically, the voltage VsN will be equal to (VRT -VCOUP-Q / CSN), where VCOUP is a coupling voltage drop across the transistor 112, Q is the charge transferred from the photodiode to the detection node SN, and CSN is the capability of the detection node SN. In the other case, if a load has been transferred to the additional node AN during the transfer operation, the voltage VsN is clamped to a level equal to VSK-VTHA differential signal AVsN is generated for example during the first operation of reading by subtracting the voltage VsN from a reset level VRsN read by the output block 122 while the signal SW is at the voltage level VSK, VRSN 25 being for example equal to VRT -VCOUP- In other words, AVSN = VRsN-VsN. Thus AVsN is equal to Q / CsN. In a subsequent operation 208, a second read operation is performed to read a VSN + AN voltage level associated with the SN detection node when connected to the additional node AN. In particular, the second read operation is performed with the control signal SW at a level higher than VSK, for example at the supply voltage VDD. Thus, the total charge transferred from the photodiode during the transfer operation is shared between the two SN and AN nodes, and the corresponding voltage on the SN detection node is read. The voltage value will then be equal to VRT -VCOUP-W (CSN + CANI-CSW), CSN being the capacity of the detection node SN, CAN being the capacity of the detection node AN, and Csw being the parasitic capacitance introduced by The transistor 112. A differential signal AVsN + AN is for example generated during the second read operation by subtracting the voltage VsN + AN from a reset level VRSN + AN read by the output block 122 while the signal SW is at the higher level at VSK, for example at the supply voltage VDD. In other words, AV - g - VSN + ANrential --- - This value will be Ale n / (CCC In a next operation 210, the signal differed AVsN based on the voltage VSN read on the detection node SN during the first This read operation is compared with a threshold level Vs. This operation is carried out, for example, by the output block 122 of FIG. 1. Of course, it will be clear to one skilled in the art that the voltage levels described in FIG. here in relation to the pixel, such as VRT, VsN, VRSN, AVsN etc., are the values associated with the pixel, which are likely to be altered by a gain chain applied by the transistor 106 and the output block 122. For example, the threshold level Vs is chosen to correspond to a value associated with the pixel equal to or less than (VRT -VCOUP) - (VSK-VTH), for example between 50 and 95% of (VRT -VCOUP) - (VSK- VTH), where VRT 25 is a reset level applied to the SN detection node If in operation 210 the voltage AVsN is determined to be lower than the threshold level Vs, the next operation is the operation 212, in which the output block 122 generates the value of the output pixel PIX on the basis of the voltage level AVsN read during the read operation. Otherwise, if in operation 210 the voltage AVsN is determined to be greater than the threshold level Vs, the next operation is the operation 214, in which the output block 122 generates the value of the output pixel PIX on the SN + AN = VRSN + AN B13328 - DD15336JBD 12 based on the AVsN_FAN voltage level read during the second read operation. For example, the pixel value PIX is then determined as equal to G.AVsNI_AN, where G is a gain. For example, the gain G equals (CsN + CAN + Csw) / CsN, CSN and CAN 5 being the capacitances on the nodes SN and AN respectively, and Csw being a capacitance associated with the transistor 112 while the signal SW is at the level of the supply voltage VDD. This value is equivalent to a full load transfer to a CSN capacitance, and thus a high sensitivity is achieved with an extended dynamic range. It will be apparent to those skilled in the art that the order of operations of FIG. 2 could be changed. For example, in some embodiments, the second read operation 208 could be performed after the comparison operation 210. In addition, although in the example of Figure 2 the second read operation is always performed, in variants of embodiment the second read operation could be performed only if during the comparison operation it is detected that the voltage level AVsN is greater than Vs. FIGS. 3A to 3E are diagrams representing the charge transfer between the nodes in the pixel of Figure 1 during reset, integration and read phases, according to an exemplary embodiment. In particular, each of the diagrams represents, from left to right, the voltage supply level of the VRT pixel, the control voltage RTG, the voltage of the photodiode PD, the control voltage TG, the voltage on the node of detection SN, the control voltage SW, the voltage on the additional node AN, and the control voltage RST. As illustrated, the voltage VRT is for example at a level below the supply voltage VDD, and the voltage level VPD at which the photodiode is fixed is for example at a level below the voltage VRT. For example, the supply voltage VDD is at a level between 3.3 and 3.6 V, the supply voltage VRT is at a level between 2.5 and 3 V, and the fixed level VPD of the photodiode is between 1 and 1.6 V. The voltage level VRT corresponds for example to the voltage level VDD minus the threshold voltage MOS VTH of the transistor 112.
    [0003] Fig. 3A shows a reset operation of the PD photodiode. In particular, the control signal RTG is for example activated at the supply voltage VDD, and any charge present on the photodiode is thus discharged to the supply rail VRT, as represented by an arrow 302. FIG. 3A also shows a voltage resetting operation on the detection node SN and on the additional node AN. Although this is represented in the same diagram as the reset of the PD photodiode, the reset of the detection node SN and of the additional node AN takes place for example at a different time, as at the end of the read operation. a previous pixel value, or just before the transfer operation if in a roller shutter operating mode. For example, the control signals RST and SW are both activated at the supply voltage VDD, so that the nodes SN and AN are both coupled to the supply voltage VRT, and set up at a voltage level represented by a line 304 in FIG. 3A, which is slightly lower than the VRT level due to the coupling voltage drop across the transistor 116. The signal SW is then reduced to the VSK level or to the ground causing a voltage drop on the detection node SN due to the coupling voltage drop across the transistor 112 at a level 30 represented by a line 306 in FIG. 3A. Figs. 3B and 30 are both a transfer operation performed at the end of the integration period. Figure 3B shows the case in which no load is transferred to the additional node AN during the transfer operation, while Figure 3C represents the case in which loads are transferred to the additional node AN. during the transfer operation. As shown in FIG. 3B, during the transfer operation, the control signal TG is brought to the supply voltage VDD, and the control voltage SW is brought to the level VSK. This causes a charge flow Q from the photodiode to the detection node SN, as represented by an arrow 310. The voltage level on the detection node SN thus drops to a level 312 which is higher than the VSK-VTH level. - Therefore, there is no charge transfer to the additional node AN. The comparison operation 210 of Fig. 2 will therefore indicate that the AVsN voltage level is below the threshold level Vs, and thus the pixel value PIX will be determined in the operation 212 on the basis of the read voltage. during the first read operation. As in FIG. 3E, in the example of FIG. 3C, the conutant signal TG is brought to the supply voltage VDD, and the control voltage SW is brought to the VSK level during the transfer operation. This causes a charge flow Q of the photodiode to the detection node SN as represented by an arrow 310. However, this time there is more charge, which causes a drop in the voltage level on the detection node. SN at a level 314 equal to VSK-VTH. Charges are therefore transferred to the additional node AN, as represented by an arrow 316, and the voltage on the additional node AN thus drops to a level 318. The comparison operation 210 of FIG. that the voltage level AVsN is greater than the threshold level Vs, and thus the pixel value PIX will be determined in the operation 214 on the basis of the voltage read during the second read operation. Figs. 3D and 3E both represent the step of fully activating transistor 112 just prior to the second read operation, for example, by feeding the signal B13328 - DD15336JBD SW at voltage level VDD. As represented by different widths of the columns in the example of FIG. 30, the additional node AN has for example a capacity greater than that of the detection node SN. FIG. 3D corresponds to the case of FIG. 3E, in which no load has been transferred to the additional node AN during the transfer operation. Thus the load on the detection node SN is shared between the nodes SN and AN, and the voltage drops to a level represented by a line 320. FIG. 3E corresponds to the case of FIG. 30, in which charges have been transferred. to the additional node AN during the transfer operation. Thus, the voltages on the nodes SN and AN are equalized at a level represented by a line 322, greater than the level 320 of FIG. 3D. FIG. 4 is a graph illustrating an example of the relationship between the charge level Q accumulated by the photodiode during the integration period and the corresponding differential signal AV detected on the detection node SN during the first or the second operation of FIG. reading. As represented by a solid line 402, up to a charge level Q 'corresponding to a voltage change AVsN1 = VRSN- (VSK-VTH) on the detection node SN, no load will be transferred to the additional node AN and the voltage value read during the first read operation will be proportional to the load Q. The slope of the line 402 is, for example, a function of 1 / CSN, where CSN is the capacity of the detection node SN . The pixel value PIX is calculated on the basis of the first read operation 30 only if the load Q is less than a level Q. This load level corresponds to a change of voltage AV1 read during the first read operation equal to the Thus, if the charge accumulated by the photodiode is between 0 and Qs, the pixel value PIX will be between 0 and AV1. 3328 - DD15336JBD 16 Conne this is represented by a solid line 404, the voltage change AVsNA_AN detected during the second reading operation will be proportional to the load Q with a slope that is a function of 1 / (CsN + CAN + Csw ), where CSN and CAN are the capabilities of the SN and AN nodes respectively, and Csw is the capacity associated with the switch 112 when the control signal SW is at the voltage level VDD. The voltage change AVsNA_AN detected during the second read operation is for example limited to a level AVmAx = - QMAX * (CSNI-CANI-CSW), where QmAx is the maximum level of charge that can be transferred from the photodiode. The dotted line 406 in FIG. 4 represents an example of the PIX pixel value calculated for a given load level of Qs or more, which is calculated by applying a gain G to the value read along the line 404, the gain G corresponding, for example, to the gain value G mentioned above and being equal to (CSN + CAN + Csw) / CsN. The slope of the dash line 406 is for example substantially the same as that of the solid line 402, so that there is a substantially linear relationship between the accumulated charge and the pixel value PIX. Figure 5 schematically illustrates the output block 122 of Figure 1 in more detail according to an exemplary embodiment. The column line 110 is for example coupled to ground via a current source 501. In addition, the column line 110 is coupled through a switch 502 controlled by a signal of sampling SSN, at a node 504. The node 504 is in turn coupled to ground via a capacitor 506, and an analog-to-digital converter and processing block (ADC + P) 508.
    [0004] Similarly, the column line 110 is for example coupled, via respective switches 512, 514 and 516, controlled by sampling signals SRsN, SsN + AN and SRSN + AN respectively, to respective nodes 518. , 520 and 522. The nodes 518, 520 and 522 are in turn coupled to ground through capacitors 524, 526 and 528 respectively, and to block 508. As will be described in more detail hereinafter with reference to FIG. 6, the sampling signals SsN, SRSN, SSN + AN, SRSN + AN are activated to sample the voltage present on the detection node SN 5 of a selected pixel of the column, and the voltages read are stored by the capacitors 506, 524, 526 and 528. The block 508 for example converts each of the sampled voltages into a digital value, and the pixel output value PIX is for example generated on the basis of these numerical values. . The PIX pixel values are for example stored in an image memory (MEM) 530. It will be apparent to those skilled in the art that in some embodiments the output block 122 of FIG. other circuits for conditioning the input signals and the multiplexing signals before supplying them to the block 508. Fig. 6 is a timing diagram showing examples of the timing signal CLK supplied to the control block 120, RTG control signals , TG, RST, SW and RD in the pixel of FIG. 1 for a row of pixels of rank (i-1), for a row of rank i, and for a rank row (i + 1), and also sampling signals SsN, SRsN, SsN + AN and SRsN + AN which for example control the switches of the output block 122 to sample the voltage on the column line 110. The example of Figure 6 assumes that the transistor reset 116 is connected to the additional node AN, rather than the node of SN detection. The manner in which the read sequence could be changed in the event that the reset transistor 116 is connected instead to the SN detection node will be clear to those skilled in the art. In addition, the example of Fig. 6 also assumes a global shutter operation using the transfer gate 118. The manner in which a pull-down shutter operation could be achieved with or without the transfer gate 118 will be apparent to the user. skilled in the art. In particular, the implementation of a rolling shutter involves a shift of the integration periods of the pixels of each row relative to one another so that each row can be read shortly. after the end of its corresponding integration period.
    [0005] With reference to FIG. 6, initially, all the signals are for example at ground level, except the signal SW. The signal SW is for example permanently at the VSK level, except during the second read operation as described above, and except during the integration period as described below. During the photodiode reset operation (RESET PD), the photodiodes of the entire image sensor are, for example, reset to initiate a global integration period. Thus, each of the RTGi_l, RTGi and RTGi + 1 signals has a high pulse occurring shortly after a high pulse of the CLK timing signal. The reset signals RSTi_i, RSTi and RSTi + 1, and the signals SWi_i, SW i and SWi + 1, are all for example high throughout the integration period. The integration period has for example a duration tiNT, and at the end of the integration period, the global shutter operation (TRANSFER) is for example performed to transfer, at the same time in each pixel of the sensor d image, the charge from the photodiode to the detection node SN. Thus, each of the signals TGi_i, TG i and TGi_11 has a high pulse occurring shortly after another high pulse of the synchronization signal CLK. The rows of pixels are for example read one by one in a scrolling manner, as shown by an arrow 602 in FIG. 6. In the example of FIG. 6, the reading sequence always involves a reading of the two voltages. VsN and VsN + AN, and both VRSN and VRSN + AN reset levels. The read sequence of row i-1 takes place first in FIG. 6, and involves an initial activation of read signal RDi_1. The SsN sampling signal is then activated, and the first read operation is performed, to read the voltage level VsN on the detection node SN. The signal SWi_i is then brought from the level VSK to the level of the supply voltage VDD, and the second read operation is performed by activating the sampling signal SsN + AN to read the voltage VsN + AN on the detection node SN. The reset signal RSTi_i is then activated at the VDD level to reset the voltage on the SN and AN nodes, and the sampling signal SRsNi_AN is activated to cause the reading of the voltage level VsN + AN on the SN and AN nodes. The signal SsN + AN is also for example activated to preload the sampling capacitor corresponding to the reset level. The signal SW is then brought back to the VSK level, and the SRSN sampling signal is activated to read the reset value VRsN on the detection node SN. The signal SsN is also for example activated to preload the sampling capacitor corresponding to the reset level. The reading sequences of the rows i and (i + 1) are for example identical.
    [0006] Although in the example of FIG. 6 the control signal SW remains at the level of VSK except during the integration and read operation, in alternative embodiments it could be brought to a lower level such as the mass level. most of the time, except during transfer and read operations. One advantage of bringing the signal SW to a lower voltage level is that the voltage on the detection node SN will be better preserved. An advantage of the embodiments described herein is that a pixel of an image sensor is capable of having both high dynamic range and high sensitivity in a relatively simple manner and without significantly increasing the size and power consumption of the pixel. Indeed, by providing an additional node coupled to the detection node via a transistor controlled by an intermediate voltage during the transfer phase, the gain at the level of the detection node is variable as a function of the amount of charge accumulated by the photodiode during the integration period. With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example, although the described embodiments include a transfer gate 118 providing a simple overall shutter implementation, it will be apparent to those skilled in the art that in alternative embodiments this transfer gate could be omitted. In addition, it will be apparent to those skilled in the art that rather than being at 0V, the ground voltage could be considered to be another supply voltage that could be at any level, such as a level. negative. In addition, it will be apparent to those skilled in the art that in all the embodiments described herein, some or all of the NMOS transistors could be replaced by PMOS transistors and vice versa. In addition or instead, some transistors like transistor 112 could be replaced by NMOS / PMOS switches. In addition, although transistors based on MOS technology have been described here, in alternative embodiments other transistor technologies, such as bipolar technology, could be used.
    [0007] In addition, it will be apparent to those skilled in the art that the various elements described in connection with the various embodiments could be combined, in alternative embodiments, in any combination.
    权利要求:
    Claims (15)
    [0001]
    REVENDICATIONS1. An image sensor comprising: at least one pixel having a photodiode (PD); a detection node (SN) coupled to the photodiode via a transfer gate (104); and another node (AN) coupled to the detection node (SN) via a first transistor (112); and a control circuit (120) adapted to: apply, during a reset operation of the voltage levels on the detection node (SN) and the other node (AN), a first voltage level wm at a node of controlling the first transistor (112); and applying, during a charge transfer operation from the photodiode (PD) to the detection node (SN), a second voltage level (VSK) at the control node of the first transistor (112), the second level voltage being lower than the first voltage level and greater than a ground voltage of the pixel.
    [0002]
    The image sensor of claim 1, wherein the second voltage level (VSK) is less than VRTI-VTH and greater than VPD-I-VTH, where VRT is a reset voltage level applied to the node of detection (SN) and at the other node (AN) during the reset operation, VPD is a fixed voltage level of the photodiode and VTH is a threshold voltage level of the first transistor (112). 25
    [0003]
    An image sensor according to claim 1 or 2, wherein during the transfer operation the control circuit (120) is further adapted to apply the first onm voltage level to a control node of the control gate. transfer (104).
    [0004]
    An image sensor according to any one of claims 1 to 3, wherein the control circuit (120) is further adapted to: perform, after the transfer operation, a first read operation to generate a first value (AVsN) based on the voltage on the detection node (SN); and comparing the first value (AVsN) to a threshold level (Vs).
    [0005]
    An image sensor according to claim 4, wherein the control circuit (120) is further adapted to perform a second read operation to generate a second value (AVSNUN) based on the voltage on the detection node. during the application of the first voltage level to the control node of the first transistor (112).
    [0006]
    An image sensor according to claim 5, further comprising an output block (122) coupled to the detection node via a read circuit (106, 108) of the pixel, wherein on the base from comparing the first value to the threshold level (Vs), the output block (122) is arranged to: generate a pixel value (PIX) based on the first value; or generate a pixel value (PIX) based on the second value.
    [0007]
    An image sensor according to any one of claims 1 to 6, wherein said at least one pixel further comprises a reset transistor (116) having one of its main current nodes connected to the other node (AN) and its other main current node coupled to a supply voltage rail.
    [0008]
    An image sensor according to any one of claims 1 to 6, wherein said at least one pixel further comprises a reset transistor (116) having one of its main current nodes connected to the sense node ( SN) 30 and its other main current node coupled to a supply voltage rail.
    [0009]
    An image sensor according to any one of claims 1 to 8, wherein said at least one pixel further comprises a second transfer gate (118) coupled between the photodiode (PD) and a supply voltage rail.
    [0010]
    An image sensor according to claim 9, wherein the control circuit (120) is adapted to control the second transfer gate (118) of said at least one pixel to reset the photodiode (PD) to perform a global reset of the photodiode (PD). image sensor.
    [0011]
    11. A method for operating at least one pixel of an image sensor, said at least one pixel comprising: a photodiode (PD) 10; a detection node (SN) coupled to the photodiode via a transfer gate (104); and another node (AN) coupled to the detection node (SN) via a first transistor (112), the method comprising: - applying, by a control circuit (120) during a reset operation of voltage levels on the detection node (SN) and the other node (l- N), a first voltage level (VDD) on a control node of the first transistor; and - applying, by the control circuit (120) during a charge transfer operation from the photodiode (PD) 20 to the detection node (SN), a second voltage level (VSK) at the control node of the first transistor (112), the second voltage level being lower than the first voltage level and greater than a ground voltage of the pixel.
    [0012]
    The method of claim 11, wherein the second voltage level cvslq is less than VRT + VTH and greater than VPDA-VTH, where VRT is a reset voltage level applied to the sense node (SN) and the Another node (AN) during the reset operation, VPD is the fixed voltage level of the photodiode and VTH is a threshold level of the first transistor (112).
    [0013]
    The method of claim 11 or 12, further comprising applying, during the transfer operation, the first voltage level (VDD) to the transfer gate (104).
    [0014]
    The method of any one of claims 11 to 13, further comprising: performing, after the transfer operation, a first read operation to generate a first value (AVsN) based on the voltage on the node detection (SN); and comparing the first value (AisN) to a threshold level (Vs).
    [0015]
    The method of claim 14, further comprising: a second read operation for generating a second value (AVsm_AN) based on the voltage on the sense node during the application of the first voltage level to the control node the first transistor (112); and based on the comparison of the first value at the threshold level (Vs): generating a pixel value (PIX) based on the first value; or generate a pixel value (PIX) based on the second value.
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    2016-04-22| PLSC| Publication of the preliminary search report|Effective date: 20160422 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1460106A|FR3027479B1|2014-10-21|2014-10-21|PIXEL OF IMAGE SENSOR HAVING MULTIPLE SENSING KNOT GAINS|FR1460106A| FR3027479B1|2014-10-21|2014-10-21|PIXEL OF IMAGE SENSOR HAVING MULTIPLE SENSING KNOT GAINS|
    EP15190265.7A| EP3013037B1|2014-10-21|2015-10-16|Pixel of image sensor having multiple detection node gains|
    US14/918,195| US9736411B2|2014-10-21|2015-10-20|Image sensor pixel having multiple sensing node gains|
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